Image Data Quantization Table Pre - Process 4 x 4 Block JPEG Compression Flow Quantization Transform Zig - Zag DCT Run - Length Encoding Quantization

This paper presents an uniied approach for partitioning and synthesizing high-level design speciications onto dynamically reconngurable multi-fpga architectures. We use the Joint Photographic Experts Group (jpeg) still image compression algorithm as a design example to demonstrate the eeectiveness of our approach. Central to our approach is the sparcs (Synthesis and Partitioning for Adaptive Reconngurable Computing System) design environment that consists of a tightly integrated collection of synthesis and partitioning tools, which can generate multiple temporal conngurations of a design for any multi-fpga board architecture. We present the design ow through the sparcs system, consisting of temporal partitioning, spatial partitioning and design synthesis. We have compared two versions of the jpeg compression algorithm, one with the fpga board conngured once (static) and the other with multiple reconngurations (dynamic). The multiple board conngurations for the design example were generated using the sparcs design environment. The results presented in the paper show that the dynamically reconngured version of the jpeg compression algorithm achieves considerable improvement in execution times for several still image les of varying sizes.